A “MONOS” (Metal Oxide Nitride Oxide Semiconductor) structure is used for a non-volatile memory device. According to a MONOS structure, for example, an ONO (nitride layer is formed between two of oxide layers) layer is formed between a substrate and a gate electrode. The nitride layer in the ONO layer traps (stores) a large amount of charge. Trapping and releasing of charges allows the non-volatile memory to function as a memory device properly.
In order to perform writing/reading operation, electrons are stored and removing on a bottom entire surface of a gate electrode using tunneling current. Another way to perform writing/reading operation, hot carrier is used. According to the way of using tunneling current, a large number of writing operation can be carried out and a higher reliability can be obtained. On the other hand, according to the way of using hot carrier, operation voltage for writing and deleting is low and operation speed is high.
FIG. 1 shows a structure of a conventional semiconductor memory device. In FIG. 1, a memory cell region is shown at the left side while a peripheral circuit region (transistor which does not form a memory cell) is shown at the right side. According to the conventional memory device, shown in FIG. 1, two-bit data can be stored in a single cell. Electrons are stored or trapped at the right and left sides of an ONO (Oxide-Nitride-Oxide) layer 16, 18, 20, which is formed on the right and left sides of a gate electrode.
When storing electrons in a charge storage layer 18, a source and a substrate are grounded, while a gate and a drain are applied with a high voltage. In this stage, since a strong electric field in a transverse direction is generated around the drain, and electrons passed through a channel get in a high-energy condition (hot electrons), those hot electrons get close to (pulled toward) an electric field in a vertical direction generated around the gate electrode. When reading data, electrons are stored in a nitride layer 18 of the ONO layer, formed at a lower portion of a side wall, so that a resistance value of an n− layer, formed at a lower portion of the ONO layer, is changed. As a result, the read data can be distinguished between “1” and “0”.
In structure, as shown in FIG. 1, an N+ region 12 and an N− region 14 are formed in a surface area of a silicon substrate 10. A silicon oxide layer 16, a poly-silicon layer 22, WSi layer 24 and a SiN layer 26 are formed on the silicon substrate 10. A nitride layer 18, a silicon oxide layer 20 and an insulating layer 28 are formed (layered) on a sidewall of the gate electrode. Those layers 18, 20 and 28 are used for storing electric charge.
Next, the structure of a peripheral circuit region (not a memory cell region) is described. An N+ region 12 and an N− region 14 are formed in a surface area of a silicon substrate 10, in the same manner as the memory cell region. A silicon oxide layer 16, a poly-silicon layer 22, WSi layer 24 and a SiN layer 26 are formed on the silicon substrate 10. A silicon oxide layer, a NSG layer 30, a nitride layer 18 for storing electric charge, a silicon oxide layer 20 and an insulating layer 28 are formed (layered) on a sidewall of the gate electrode.
FIGS. 2 to 6 show fabrication steps of a conventional non-volatile memory device, shown in FIG. 1.
Firstly, a silicon oxide layer 32, a poly-silicon layer 22, a WSi layer 24 and a silicon nitride layer 26 are formed on a silicon substrate 10.
Next, a gate electrode is shaped by a lithographic process. Subsequently, the silicon nitride layer 26 is etched by a dry-etching process. After that, the WSi layer 24 and the poly-silicon layer 22 are dry-etched.
Next, a resist layer is removed by an ashing process and wet-washing process to form a gate electrode, as shown in FIG. 2. After that, ions are implanted into the silicon substrate 10 to form an N− region 14.
Next, a silicon oxide layer 16 is formed by a thermal oxidation process, as shown in FIG. 3. After that, an NSG layer 30 is formed at a surface area of the silicon oxide layer 16.
Next, as shown in FIG. 4, a part of the NSG layer 30 located in a memory cell region is removed by a photo-lithography process and an etching process. At this time, a part of the NSG layer 30 located in a peripheral circuit region is not removed but remained.
Next, as shown in FIG. 5, a SiN layer 18 is formed on an oxide layer 16 in the memory cell region by a CVD process, while a SiN layer 18 is formed on an NSG layer 30 in the peripheral circuit region by a CVD process. After that, an oxide layer 20 is formed on the SiN layer 18.
Next, as shown in FIG. 6, both in the memory cell region and peripheral circuit region, a SW insulating layer 28 is formed on the oxide layer 20 by a CVD and a dry-etching process.
Subsequently, a NSG layer 36, which is to be used as a mask in a high-density implantation process, is formed on the entire surface including a sidewall 28. The NSG layer 36 may be formed to have a thickness of 100 angstroms (Å) by a CVD process. Next, an N+ layer 12 is formed in a source/drain region of the memory cell region by a photolithography-implantation process. Next, an N+ layer 12 is formed in a source/drain region of the peripheral circuit region by a photolithography-implantation process. A type of impurity to be ion-implanted is selected according to the type of transistors (N or P). After that, as shown in FIG. 1, the NSG layer 36 is removed.
According to the above-described conventional semiconductor device, the nitride layer 18 for storing charge is remained in a peripheral circuit region (not a memory cell region), so that electrons are stored not only in a transistor forming the memory cell region but also in a transistor forming the peripheral circuit. As a result, a hot-carrier characteristic of a transistor in the peripheral circuit is deteriorated.
For that reason, an electric-erasing process is carried out to delete electrons from the nitride layer 18 for storing charge. However, electrons are remained in a part of the nitride layer 18 located above a LDD (14) after the electric-erasing process. As a result, a current value after the erasing process becomes lower than that prior to the erasing process.
A patent publication 1 (JP2007-157874A) describes a non-volatile memory device, which is not material to the present invention.
[Patent Publication 1] JP2007-157874A
A patent publication 2 (JP2004-343014A) describes a non-volatile memory device, in which a depressed portion is formed at an end of a lower part of a gate electrode. However, the publication does not describe the relation between a memory cell region and a peripheral circuit region.
[Patent Publication 2] JP2004-343014A